// Copyright (C) 1953-2023 NUDT
// Verilog module name - forward_mode_lookup
// Version: V4.3.0.20230322
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//          
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module forward_mode_lookup
(
       i_clk,
       i_rst_n,
       
       iv_desp,
       i_desp_wr,
       
       ov_ram_raddr,
       o_ram_rd,

       ov_desp,
       o_desp_wr
);

// I/O
// clk & rst
input                  i_clk  ;                   //125Mhz
input                  i_rst_n;
// descriptor from p0
input      [87:0]      iv_desp  ;
input                  i_desp_wr;
// read addr to RAM
output reg [5:0]       ov_ram_raddr;
output reg             o_ram_rd;
// pkt_bufid and pkt_type and outport to forword
output reg [87:0]      ov_desp;
output reg             o_desp_wr;

//////////////////////////////////////////////////
//      extract flow_id and lookup table        //
//////////////////////////////////////////////////
reg  [87:0]  rv_desp_1;
reg          r_desp_wr_1;
reg  [87:0]  rv_desp_2;
reg          r_desp_wr_2;
always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin       
        ov_ram_raddr            <= 6'h0;
        o_ram_rd                <= 1'h0;
        
        rv_desp_1                 <= 88'b0;
        r_desp_wr_1               <= 1'b0;     
    end                        
    else begin
        if(i_desp_wr == 1'b1)begin
            ov_ram_raddr    <= iv_desp[42:37];//inport
            o_ram_rd        <= 1'h1;
            
            rv_desp_1       <= iv_desp;
            r_desp_wr_1     <= i_desp_wr; 
        end
        else begin
            ov_ram_raddr            <= 6'h0;
            o_ram_rd                <= 1'h0;
            
            rv_desp_1               <= 88'b0;
            r_desp_wr_1             <= 1'b0;
        end
    end
end

always @(posedge i_clk) begin// this signal have to delay 2 cycle,beacuse of the read ram data had wait two cycle
    rv_desp_2                 <= rv_desp_1;
    r_desp_wr_2               <= r_desp_wr_1;
    
    ov_desp                   <= rv_desp_2;
    o_desp_wr                 <= r_desp_wr_2;          
end

endmodule